1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device that includes a high frequency wiring.
2. Description of Related Art
There is a well-known technique that forms a multilayer wiring structure by forming at first such recesses as wiring grooves, via-holes, etc. in an interlayer insulation film, then by filling the recesses with a metal material and by removing the metal material exposed outside the recesses by a CMP (Chemical Mechanical Polishing) process or the like, thereby forming wirings and via-holes. In case of such a technique, if any density difference exists among those formed wirings and via-holes, then hollows and dents referred to as erosion and dishing often come to appear in the CMP process. And this might result in variation of the in-plane film thickness in the CMP process. In order to prevent the occurrence of such erosion and dishing in the CMP process, dummy metals are used. The dummy metals are disposed at a fixed density and of electrically floating state. The dummy metals are thus provided as layers other than wirings provided to flow a current. Providing such dummy metals makes it easier to manufacture semiconductor devices.
When dummy metals are placed between a high frequency wiring of an inductor, transformer, or the like and the semiconductor substrate, however, the capacitance between the semiconductor substrate and the high frequency wiring increases in accordance with the thickness of the dummy metals, since the capacitance is determined by the series of the capacitance determined by a distance between the high frequency wiring and the dummy metals and the capacitance determined by a distance between the dummy metals and the semiconductor substrate. Consequently, the characteristics of the inductor and the transformer are degraded. This has been a problem.
The patent document 1 (Japanese Unexamined Patent Application Publication No. 2002-110908) describes a configuration having a convex portion formed in a region except for the region just under a spiral linear conductor layer. The convex portion constitutes a dummy element region.
The patent document 2 (Japanese Unexamined Patent Application Publication No. 2005-285970) describes a configuration that does not dispose any conductive pattern in a region having such functional elements as an inductor. The structure can avoid the influence by the conductive pattern to be exerted on those functional elements. Moreover, dummy patterns are disposed in a region surrounding the functional elements disposed region. By using such structures, the flatness of the surface after a CMP process can be improved.
The patent document 3 (Japanese Unexamined Patent Application Publication No. 2003-37111) describes a configuration having a metal film that has a specific pattern formed in a no-real-wiring-provided region on a semiconductor device. In a region having two metal wirings formed in parallel, the metal film is disposed so as to be separated from the region by a distance longer than a predetermined distance.